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參數(shù)資料
| 型號： | MC74HC646N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal 3-State Bus Transeceivers and D Flip-Flops |
| 中文描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 328K |
| 代理商： | MC74HC646N |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
! "
High–Performance Silicon–Gate CMOS
The MC54/74HC646 is identical in pinout to the LS646. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
These devices are bus transceivers with D flip–flops. Depending on the
status of the Data–Source Selection pins, data may be routed to the outputs
either from the flip–flops or transmitted real–time from the inputs (see
Function Table and Application Information).
The Output Enable and the Direction pins control the transceiver’s
function. Bus A and Bus B cannot be routed as outputs to each other
simultaneously, but can be routed as inputs to the A and B flip–flops. Also,
the A and B flip–flops can be routed as outputs to Bus A and Bus B.
Additionally, when either or both of the ports are in the high–impedance
state, these I/O pins may be used as inputs to the D flip–flops for data
storage.
The user should note that because the clocks are not gated with the
Direction and Output Enable pins, data at the A and B ports may be clocked
into the storage flip–flops at any time.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 780 FETs or 195 Equivalent Gates
LOGIC DIAGRAM
A
DATA
PORT
B
DATA
PORT
A0
A1
A2
A3
A4
A5
A6
A711
10
9
8
7
6
5
4
20
19
18
17
16
15
14
13
B0
B1
B2
B3
B4
B5
B6
B7
21
3
1
23
2
22
A–TO–B SOURCE
B–TO–A SOURCE
B–TO–A CLOCK
A–TO–B CLOCK
DIRECTION
OUTPUT ENABLE
FLIP–FLOP
CLOCKS
DATA SOURCE
SELECTION
INPUTS
PIN 24 = VCC
PIN 12 = GND
PIN ASSIGNMENT
A2
A0
DIRECTION
A–TO–B
SOURCE
A–TO–B
CLOCK
A4
A3
A1
B0
OUTPUT ENABLE
B–TO–A
SOURCE
CLOCK
B–TO–A
B5
B4
B3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
B7
B6
B2
B1
A7
GND
A6
A5
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
1
24
J SUFFIX
CERAMIC PACKAGE
CASE 758–02
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
1
24
1
24
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