參數(shù)資料
型號(hào): MC74HC4351AN
廠商: MOTOROLA INC
元件分類: 運(yùn)動(dòng)控制電子
英文描述: ECONOLINE: RU - Twin Independent Outputs- Output/Output Isolation 1kVDC- Power Sharing on Outputs- Input/Output Isolation 1kVDC- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No Extern. Components Required- Custom Solutions Available- Efficiency t
中文描述: 8-CHANNEL, SGL ENDED MULTIPLEXER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 2/13頁
文件大?。?/td> 294K
代理商: MC74HC4351AN
MC74HC4351A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
LOGIC DIAGRAM
MC74HC4351A
Single–Pole, 8–Position Plus Common Off and Address Latch
FUNCTION TABLE
MC74HC4351
Control Inputs
Enable
1
2
C
L
L
L
L
L
L
L
L
H
X
L
X
X = don’t care
* When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
ON
Select
B
L
L
H
H
L
L
H
H
X
X
Channel
(LE = H)*
X0
X1
X2
X3
X4
X5
X6
X7
No e
None
A
L
H
L
H
L
H
L
H
X
X
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
X
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
VCC
– 0.5 to 14.0
– 7.0 to + 0.5
VEE
VIS
Lead Temperature, 1 mm from Case for
10 Seconds
(Plastic DIP or SOIC Package)
Negative DC Supply Voltage (Ref. to GND)
Analog Input Voltage
SOIC or TSSOP Package
V
V
V
Power Dissipation in Still Air,
500
mW
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
ranges indicated in the Recom-
mended Operating Conditions.
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused Analog I/O pins may be left
open or terminated. See Applica-
tions Information.
MULTIPLEXER/
DEMULTIPLEXER
17
18
19
16
1
6
2
5
X0
X1
X2
X3
X4
X5
X6
X7
ANALOG
INPUTS/OUTPUTS
4
X
COMMON
OUTPUT/INPUT
CHANNEL
ADDRESS
LATCH
13
12
B
C
15
A
11
7
8
LATCH ENABLE
ENABLE 1
ENABLE 2
SWITCH
ENABLES
PIN 20 = VCC
PIN 9 = VEE
PIN 10 = GND
PINS 3, 14 = NC
CHANNEL–SELECT
INPUTS
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