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參數(shù)資料
型號： MC74HC4060ADR2G
廠商： ON Semiconductor
文件頁數(shù)： 7/13頁
文件大?。?/td> 0K
描述： IC COUNTER OSC 14STAGE 16SOIC
標(biāo)準(zhǔn)包裝： 1
系列： 74HC
邏輯類型： 二進(jìn)制計數(shù)器
方向： 上
元件數(shù)： 1
每個元件的位元數(shù)： 14
復(fù)位： 異步
計數(shù)速率： 50MHz
觸發(fā)器類型： 負(fù)邊沿
電源電壓： 2 V ~ 6 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： MC74HC4060ADR2GOSDKR
MC74HC4060A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature Range
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.5*
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature Range, All Package Types
– 55
+ 125
_C
tr, tf
Input Rise/Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
1000
500
400
ns
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at
2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
V
Guaranteed Limit
Unit
55 to 25°C
≤85°C
≤125°C
VIH
Minimum HighLevel Input Voltage
Vout = 0.1V or VCC 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum LowLevel Input Voltage
Vout = 0.1V or VCC 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum HighLevel Output Voltage
(Q4Q10, Q12Q14)
Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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