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參數(shù)資料
| 型號(hào)： | MC74HC4049D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Hex Buffers/Logic-Level Down Converters |
| 中文描述： | HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 191K |
| 代理商： | MC74HC4049D |
MC54/74HC4049 MC54/74HC4050
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
17
26
6.0
13
21
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
27
pF
Figure 1a. Switching Waveforms (HC4049)
Figure 1b. Switching Waveforms (HC4050)
INPUT A
tPLH
tPHL
tr
tf
VCC
GND
tTHL
tTLH
OUTPUT Y
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
tr
tf
GND
tPHL
tPLH
tTLH
tTHL
10%
590%
10%
50%
90%
50%
10%
10%
90%
INPUT A
OUTPUT Y
VCC
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