SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
!
High–Performance Silicon–Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the
MC54/74HC4050 consists of six noninverting buffers. They are identical in
pinout to the MC14049UB and MC14050B metal–gate CMOS buffers. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The input protection circuitry on these devices has been modified by
eliminating the VCC diodes to allow the use of input voltages up to 15 volts.
Thus, the devices may be used as logic–level translators that convert from a
high voltage to a low voltage while operating at the low–voltage power
supply. They allow MC14000–series CMOS operating up to 15 volts to be
interfaced with High–Speed CMOS at 2 to 6 volts. The protection diodes to
GND are Zener diodes, which protect the inputs from both positive and
negative voltage transients.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 5
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)
24 FETs or 6 Equivalent Gates (4050)
LOGIC DIAGRAMS
Y0
A0
A1
A2
A3
A4
A5
Y1
Y2
Y3
Y4
Y5
7
9
11
14
2
4
6
10
12
15
PIN 1 = VCC
PIN 8 = GND
PINS 13, 16 = NO CONNECTION
HC4049
(INVERTING BUFFER)
Y0
A0
A1
A2
A3
A4
A5
Y1
Y2
Y3
Y4
Y5
7
9
11
14
2
4
6
10
12
15
HC4050
(NONINVERTING BUFFER)
5
3
PIN ASSIGNMENT
FUNCTION TABLE
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Y4
NC
A5
Y5
NC
A3
Y3
A4
Y1
A0
Y0
VCC
GND
A2
Y2
A1
A
Y Outputs
HC4049
Input
HC4060
L
H
H
L
L
H
NC = NO CONNECTION
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
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16