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參數(shù)資料
| 型號： | MC74HC4024N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 7-Stage Binary Ripple Counter |
| 中文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 7-BIT UP BINARY COUNTER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 173K |
| 代理商： | MC74HC4024N |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC74HC4024 is identical in pinout to the standard CMOS MC14024.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of 7 master–slave flip–flops. The output of each
flip–flop feeds the next and the frequency at each output is half that of the
preceding one. The state of the counter advances on the negative going
edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the HC4024 for
some designs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 206 FETs or 51.5 Equivalent Gates
LOGIC DIAGRAM
CLOCK
RESET
1
2
3
4
5
6
9
11
12
PIN 14 = VCC
PIN 7 = GND
PINS 8, 10 AND 13 = NO CONNECTION
Q7
Q6
Q5
Q4
Q3
Q2
Q1
FUNCTION TABLE
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
NC
Q2
Q1
NC
VCC
NC
Q3
Q6
Q7
RESET
CLOCK
GND
Q4
Q5
Clock
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs are Low
X
NC = NO CONNECTION
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
1
14
1
14
ORDERING INFORMATION
MC74HCXXXXN
MC74HCXXXXD
Plastic
SOIC
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