參數(shù)資料
型號(hào): MC74HC4017N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Decade Counter
中文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁(yè)數(shù): 8/9頁(yè)
文件大小: 224K
代理商: MC74HC4017N
MC74HC4017
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
8
OSC.
(NO FEEDBACK REQUIRED)
1/6 HC04
OUTPUT
BUFFER
(OPTIONAL TO PREVENT SPURIOUS RESET.)
VCC
HC4017
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
RESET
CLOCK
CLOCK
ENABLE
CARRY OUT
Q9
Q4
Q8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
÷
9
÷
10
TYPICAL APPLICATIONS
Figure 10.
÷
2 Through
÷
10 Circuit
C
CE
Q0
R
Q1
Q8
Q9
Figure 11. Counter Expansion
8 DECODED
OUTPUTS
HC08
FIRST STAGE
INTERMEDIATE STAGES
VCC
÷
4
÷
8
÷
5
÷
2
÷
6
÷
7
÷
3
HC4017
HC4017
HC4017
CLOCK
8 DECODED
OUTPUTS
9 DECODED
OUTPUTS
R
R
HC08
LAST STAGE
C
CE
Q0
Q1
Q8
Q9
C
CE
Q1
Q8
Q9
Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that since Reset is asynchronous, the
output pulse widths are narrow.
Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs
are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
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