TIMING REQUIREMENTS (CL = 50 pF," />
參數(shù)資料
型號(hào): MC74HC373AFELG
廠商: ON Semiconductor
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC LATCH TRANSP OCT 3ST 20SOEIAJ
產(chǎn)品變化通告: 1Q2012 Discontinuation 30/Mar/2012
標(biāo)準(zhǔn)包裝: 2,000
系列: 74HC
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2 V ~ 6 V
獨(dú)立電路: 1
延遲時(shí)間 - 傳輸: 21ns
輸出電流高,低: 7.8mA,7.8mA
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: SOEIAJ-20
包裝: 帶卷 (TR)
MC74HC373A
http://onsemi.com
5
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Figure
VCC
Volts
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
Min
Max
Min
Max
Min
Max
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
30
25
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5 0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
VCC
GND
tf
tr
INPUT D
Q
10%
50%
90%
10%
50%
90%
tTLH
tPLH
tPHL
tTHL
VCC
GND
50%
LATCH ENABLE
tPLH
tPHL
Q
tw
50%
Figure 1.
Figure 2.
Figure 3.
Figure 4.
50%
1.3 V
Q
tPZL
tPLZ
tPZH
tPHZ
10%
90%
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
Q
OUTPUT
ENABLE
50%
INPUT D
LATCH ENABLE
VCC
GND
VALID
th
tsu
50%
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