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參數(shù)資料
| 型號(hào)： | MC74HC109N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Flip-Flop with Set and Reset |
| 中文描述： | HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 186K |
| 代理商： | MC74HC109N |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
!
High–Performance Silicon–Gate CMOS
The MC74HC109 is identical in pinout to the LS109. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two J–K flip–flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low–to–high transition of the clock. Both Q and Q outputs are available from
each flip–flop.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 148 FETs or 37 Equivalent Gates
LOGIC DIAGRAM
RESET 1
J1
CLOCK 1
K1
SET 1
Q1
Q1
Q2
Q2
RESET 2
J2
CLOCK 2
K2
SET 2
5
3
4
2
1
7
6
10
9
15
14
12
13
11
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Outputs
Q
Set
Reset Clock
J
K
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
L
H
L
H
X
X
X
X
L
L
H
H
X
H
L
H*
L
L
H
H*
H
Toggle
No Change
H
No Change
L
L
* Both outputs will remain high as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
CLOCK 2
K2
J2
RESET 2
VCC
Q2
Q2
SET 2
CLOCK 1
K1
J1
RESET 1
GND
Q1
Q1
SET 1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC109ND | 制造商:Motorola Inc 功能描述: |
| MC74HC10AD | 制造商:Motorola Inc 功能描述: |
| MC74HC10ADG | 功能描述:邏輯門 TRIPLE 3-IN AND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC10ADR2G | 功能描述:邏輯門 TRIPLE 3-IN AND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC74HC10ADTG | 功能描述:邏輯門 TRIPLE 3-IN AND GATE RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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