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MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
System Design Information
1.9.6
Pull-Up/Pull-Down Resistor Requirements
The MPC7455 requires high-resistive (weak: 4.7-k
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7455 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper
device operation. For the MPC7445, 360 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE
and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the
MPC7455, 483 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:5]; the pins
that must be pulled down are: L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise, be pulled
up through a pull-up resistor (weak or stronger: 4.7–1 k
) to prevent erroneous assertions of this signal
In addition, the MPC7455 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7–1 k
) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250
(see
Table 16). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and
pull-down resistors (1 k
or less) are recommended to configure these signals in order to protect against
erroneous switching due to ground bounce, power supply noise or noise coupling.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7455
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7455 or by other receivers in the system. These signals can be pulled up
through weak (10-k
) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450
RISC Microporcessor Family Users’ Manual for more information on this mode), or they may be otherwise
driven by the system during inactive periods of the bus to avoid this additional power draw. Preliminary
studies have shown the additional power draw by the MPC7455 input receivers to be negligible and, in any
event, none of these measures are necessary for proper device operation. The snooped address and transfer
attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak
pull-down resistors. If the MPC7455 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak
pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
Table 19. Impedance Characteristics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance
Processor Bus
L3 Bus
Unit
Z0
Typical
33–42
34–42
Maximum
31–51
32–44
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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