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參數資料
| 型號： | MC7445ARX867LF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 867 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數： | 25/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7445ARX867LF |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
31
Electrical and Thermal Characteristics
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7455.
Figure 13. Alternate AC Test Load for the JTAG Interface
Figure 14 provides the JTAG clock input timing diagram.
Figure 14. JTAG Clock Input Timing Diagram
Figure 15 provides the TRST timing diagram.
Figure 15. TRST Timing Diagram
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
20
25
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
TBD
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load
(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2
RL = 50
VM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR
tJF
tJHJL
TCLK
TRST
tTRST
VM = Midpoint Voltage (OVDD/2)
VM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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