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參數(shù)資料
| 型號(hào)： | MC7445ARX733LF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 733 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 46/68頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | MC7445ARX733LF |
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50
MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
System Design Information
1.9.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7455 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in
Figure 22 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
Figure 24. PLL Power Supply Filter Circuit
1.9.3
Decoupling Recommendations
Due to the MPC7455 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7455 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7455 system, and the MPC7455 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, and GVDD pin of the MPC7455. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling Motorola microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
10002
500
400
333
285
250
200
166
Notes:
1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some
examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the
MPC7455; see Section 1.5.2.3, “L3 Clock AC Specifications,” for valid L3_CLK frequencies and for more
information regarding the maximum L3 frequency. Shaded cells do not comply with Table 10.
2. These core frequencies are not supported by all speed grades; see Table 8.
Table 18. Sample Core-to-L3 Frequencies (continued)
Core Frequency
(MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
VDD
AVDD
10
2.2 F
GND
Low ESL Surface Mount Capacitors
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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