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參數(shù)資料
| 型號： | MC7445ARX1000LG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 68/76頁 |
| 文件大?。?/td> | 1520K |
| 代理商： | MC7445ARX1000LG |
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MPC7445 Product Summary Page
Superscalar Microprocessor
The MPC7445 processor features a high-frequency superscalar G4 core capable of issuing four
instructions per clock cycle (three instructions + branch) into eleven independent execution units:
q
Four integer units (3 simple + 1 complex)
q
Double-precision floating-point unit
q
Four AltiVec units (simple, complex, floating, and permute)
q
Load/store unit
q
Branch processing unit
Compatibility and Support
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Pin compatible with the MPC7441 processor.
q
As with all processors implementing the PowerPC instruction set architecture, the MPC7445 is
compatible with the MPC7xx family of processors from Motorola.
q
Processors implementing the PowerPC architecture enjoy the broadest set of operating systems,
compilers, and development tools from third-party tool vendors belonging to Motorola's Smart
Networks Alliance.
Product Features
The MPC7445 processor's 32-bit superscalar core contains:
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Three issue (plus branch) capability
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128-bit wide vector unit -- AltiVec technology
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Integrated 256K on-chip L2 cache (twice the size of previous generation)
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Full Symmetric Multi-Processing capability (SMP)
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36-bit physical address space for direct addressability of 64 Gigabytes of memory
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Hardware and Software Tablewalk
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High-bandwidth 133 MHz 64-bit MPX Bus/60x Bus
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Twice the number of BAT registers as previous generation
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Three power-saving user-programmable modes to reduce power drawn by processor
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Parity checking support on L1 and L2 cache arrays
MPC7445 Documentation
Documentation
Application Note
ID
Name
Vendor ID Format
Size
K
Rev
#
Date Last
Modified
Order
Availability
Backside L2 Timing Analysis for PCB Design Engineers
MOTOROLA
pdf
87
0.2 5/22/2003
Designing PowerPC(TM) MPC7400 Systems
MOTOROLA
pdf
97
1.1 6/05/2003
Minimal Boot Sequence for Executing Compiled C
Programs on PowerPC(TM) Devices
MOTOROLA
pdf
270
1.2
11/11/2003
Design Checklist for Motorola PowerPC(TM)
Microprocessors
MOTOROLA
pdf
309
1.6
11/11/2003
PowerPC(TM) 60X Bus Implementation Differences
MOTOROLA
pdf
135
0.3 8/06/2003
PowerPC(TM) MPX Bus Implementation Differences
MOTOROLA
pdf
76
0.1 6/05/2003
Complex Fixed-Point Fast Fourier Transform Optimization
for Altivec(TM)
MOTOROLA
pdf
158
2.1 6/03/2003
file:///F|/imaging/BITTING/CF_PROCESS/CPL/11252003/MOTO/MPC7455EC.htm (2 of 8) [27-Nov-03 11:30:25 AM]
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