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參數(shù)資料
| 型號： | MC7445ARX1000LG |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 17/76頁 |
| 文件大?。?/td> | 1520K |
| 代理商： | MC7445ARX1000LG |
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L3_CLK to high impedance: All
other outputs
tL3CHOZ
—tL3_CLK/4
+ 2.0
—tL3_CLK/4
+ 2.0
tL3_CLK/4
+ 2.0
—tL3_CLK/4
+ 2.0
—ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising or falling edge of the input
L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency with other input setup time specifications, this
will be treated as negative input setup time.
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the MPC7455 can latch an input signal that is valid for only a short time before and
a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of L3_CLK to the midpoint of the
signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other output valid time specifications, this will be
treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched by an internal clock delayed in
phase by 90°. Therefore, there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for
approximately one L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period
after the edge it will be sampled.
8. These configuration bits allow the AC timing of the L3 interface to be altered via software. L3OH0 = L2CR[12], L30H1 = L3CR[12]. Revisions of the MPC7455
not described by this document may implement these bits differently. See Section 1.11.1, “Part Numbers Fully Addressed by This Document,” and
Section 1.11.2, “Part Numbers Not Fully Addressed by This Document,” for more information on which devices are addressed by this document.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades 8
Unit
Notes
L3OH0 = 0, L3OH1 = 0
L3OH0 = 0, L3OH1 =1
L3OH0 = 1, L3OH1 = 0
L3OH0 = 1, L3OH1 = 1
Min
Max
Min
Max
Min
Max
Min
Max
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