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參數(shù)資料
| 型號： | MC7445ARX1000LF |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 45/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | MC7445ARX1000LF |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
45
System Design Information
8.6 Substrate Capacitors for the MPC7455, 483 CBGA
Figure 23
shows the connectivity of the substrate capacitor pads for the MPC7455, 483 CBGA. All capacitors are
100 nF.
Figure 23. Substrate Bypass Capacitors for the MPC7455, 483 CBGA
9
System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7455.
9.1 PLL Configuration
The MPC7455 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
MPC7455 is shown in
Table 17
for a set of example frequencies. In this example, shaded cells represent settings
that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz
column in
Table 8
. Note that these configurations were different in devices prior to Rev F; see
Section 11.2, “Part
Numbers Not Fully Addressed by This Document
,”
for more information regarding documentation of prior
revisions.
Capacitor
Pad Number
-1
-2
C1
OV
DD
V
DD
OV
DD
OV
DD
V
DD
OV
DD
AV
DD
OV
DD
GV
DD
GV
DD
V
DD
GV
DD
GND
C2
GND
C3
GND
C4
GND
C5
GND
C6
GND
C7
GND
C8
GND
C9
GND
C10
GND
C11
GND
C12
GND
1
C3-1
C3-2
C2-2
C1-2
C1-1
C2-1
A1 Corner
C7-2
C7-1
C8-1
C9-1
C9-2
C8-2
C
C
C
C
C
C
C
C
C
C
C
C
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