參數(shù)資料
型號： MC705L16CFUE
廠商： Freescale Semiconductor
文件頁數(shù)： 58/146頁
文件大小： 0K
描述： IC MCU 8BIT EPROM 80-QFP
標(biāo)準(zhǔn)包裝： 84
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SPI
外圍設(shè)備： LCD，POR，WDT
輸入/輸出數(shù)： 16
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： OTP
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-QFP
包裝： 托盤
Functional Pin Description
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
19
1.5.3.2 External Clock
An external clock from another CMOS-compatible device can be connected to the XOSC1 input, with the
XOSC2 input not connected, as shown in Figure 1-4(b). This configuration is possible regardless of how
the oscillator is set up.
1.5.4 RESET
This pin can be used as an input to reset the MCU to a known startup state by pulling it to the low state.
When power is removed, the RESET pin contains a steering diode to discharge any voltage on the pin to
VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. An
internal RESET pin pullup resistor may be selected as a mask option. A typical pullup resistor value is 46
k
.
1.5.5 Port A (PA0–PA7)
Port A is an 8-bit I/O port. The state of any pin is software programmable and all port A lines are configured
as inputs during power-on or reset. Port A outputs may be configured as open-drain outputs and
connected to a pullup resistor by software option.
1.5.6 Port B (PB0–PB7/KWI0–KWI7)
Port B is an 8-bit input-only port that shares its lines with the key wakeup interrupt (KWI) system. Port B
has a pullup option by software option.
1.5.7 Port C (PC0/SDI, PC1/SDO, PC2/SCK, PC3/TCAP, PC4/EVI,
PC5/EVO, PC6/IRQ2, and PC7/IRQ1)
Port C is an 8-bit I/O port. The state of any pin is software programmable and all port C lines are
configured as inputs during power-on or reset. All port C lines may connect to a pullup resistor by software
option.
Bits PC0–PC2 are shared with the SSPI subsystem and may be configured as open-drain outputs.
Bit 3 is shared with the TCAP pin of timer 1 and may be configured as an open-drain output.
Bit 4 is shared with the EVI bit of timer 2 and may be configured as an open-drain output.
Bit 5 is shared with the EVO bit of timer 2 and may be configured as an open-drain output.
Bit 6 is shared with the IRQ2 input. This bit is an open-drain output-only pin configured as an
output.
Bit 7 is shared with the IRQ1 input. This bit is an open-drain output-only pin configured as an
output.
1.5.8 Port D (PD1–PD3/BP1–BP3 and PD4–PD7/FP34–FP27)
Port D is a 7-bit output-only port that shares its bits with the LCD backplane/frontplane drivers. Port D lines
are configured as LCD outputs during power-on or reset. PD1–PD3 and PD4–PD7 outputs may be
configured as open-drain outputs by a software option.
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