
Memory
Bootloader ROM
MC68HC705C8A — Rev. 3
Technical Data
MOTOROLA
Memory
$0013
Timer Status Register
(TSR)
Read:
ICF
OCF
TOF
0
Write:
Reset:
U
0
$0014
Input Capture Register
High (ICRH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
$0015
Input Capture Register
Low (ICRL)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
$0016
Output Compare Register
High (OCRH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
$0017
Output Compare Register
Low (OCRL)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
$0018
Timer Register High
(TRH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Reset initializes TRH to $FF
$0019
Timer Register Low
(TRL)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Reset initializes TRL to $FC
$001A
Alternate Timer Register
High (ATRH)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Reset initializes ATRH to $FF
$001B
Alternate Timer Register
Low (ATRL)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Reset initializes ATRL to $FC
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 3 of 4)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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