
MOTOROLA
8-24
MC68HC11PH8
TIMING SYSTEM
8
Pulse accumulator control bits are located within the PACTL, TMSK2 and TFLG2 registers, as
described in the following paragraphs.
Figure 8-4 Pulse accumulator block diagram
TOF
0
PAOVF
PAIF
0
TFLG2
RTIF
TOI
RTII
0
PAII
0
PR1
PR0
TMSK2
0
PAEN
0
PAMOD
PACTL
PAOVI
R
TR1
R
TR0
PEDGE
I4/O5
&
PACNT
1
2
PA7/
OC1/
PAI
2:1
MUX
Input buffer
and edge detector
Output buffer
&
From
DDRA7
From
OC1
ST4XCK/28 clock
(from main timer)
Overow
Enable
Clock
Interrupt
requests
Internal data bus
Disab
le
ag
setting
TPG
156