參數(shù)資料
型號： MC68MH360VR25L
廠商： Freescale Semiconductor
文件頁數(shù)： 98/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
2.4 Channel-Specic Parameters
The channel-specic parameters are located in the lower part of the dual-ported RAM. Each
channel occupies 64 bytes of parameters. Physical time slots can be matched to logical
channels in several combinations. Unused logical channels leave a hole in the channel-
specic parameters that can be used for buffer descriptors for the other SCCs.
The channel-specic area determines the operating mode—HDLC or transparent. Several
entries take on different meanings depending on the protocol chosen.
2.4.1 Channel-Specic HDLC Parameters
Table 2-4 describes the channel-specic HDLC parameters. Boldfaced parameters must be
initialized by the user.
Table 2-4. Channel-Specific HDLC Parameters
Offset
Name
Width
(Bits)
Description
00
TBASE
16
Tx buffer descriptor base address—Offset of the channel’s transmit buffer
descriptor table relative to MCBASE, host-initialized. See Figure 2-2.
02
CHAMR
16
Channel mode register. See Section 2.4.1.1, “CHAMR—Channel Mode Register
(HDLC).”
04
TSTATE
32
Tx internal state —TSTATE denes the internal Tx state.
Host-initialized to 0x3800
_0000—FC = 8, Motorola mode for MH360.
Host-initialized to 0x3000
_0000— AT = 0, Motorola mode for 860MH.
Initialize before enabling the channel. See Section 2.4.1.2, “TSTATE—Tx Internal
State (HDLC).”
08
—
32
Tx internal data pointer—Points to current absolute address of channel.
0C
TBPTR
16
Tx buffer descriptor pointer (host-initialized to TBASE before enabling the channel
or after a fatal error before reinitializing the channel again)—Offset of current BD
relative to MCBASE. See Table 2-1. MCBASE + TBPTR gives the address for the
BD in use.
0E
—
16
Tx internal byte count—Number of remaining bytes
10
TUPACK
32
(Tx Temp) Unpack 4 bytes from 1 long word
14
ZISTATE
32
Zero-insertion state (host-initialized to 0x0000
_0100 for HDLC or transparent
operation)—Contains the previous state of the zero-insertion state machine.
18
TCRC
32
Temp transmit CRC—Temp value of CRC calculation result
1C
INTMSK
16
Channel’s interrupt mask ags—See Section 2.4.1.3, “INTMSK—Interrupt Mask
(HDLC).”
1E
BDFlags
16
Temp
20
RBASE
16
Rx buffer descriptor offset (host-initialized)— Denes the offset of the channel’s
receive BD table relative to MCBASE (64-Kbyte table). See Figure 2-2.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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