參數(shù)資料
型號： MC68MH360VR25L
廠商： Freescale Semiconductor
文件頁數(shù)： 121/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 4. QMC Exceptions
4.1.1 Global Underrun (GUN)
The QMC performs the following actions when it detects a GUN event:
Transmits an abort sequence of minimum sixteen 1’s in each time slot.
Generates an interrupt request to the host (if enabled) and sets the GUN bit in the
SCCE register.
Stops reading data from buffer.
Sends IDLEs or FLAGs in all time slots depending on channel mode settings until
the host does the following:
Host initializes all transmitting channels and time slots by preparing all buffer
descriptors for transmission (R bits are set) and setting the POL bit. No other re-
initialization is needed.
4.1.2 Global Overrun (GOV) in the FIFO
A global overrun affects all channels operating from an SCC. Following GOV, the QMC
performs the following:
Updates the RSTATE register to prevent further reception on this channel. Bit 20 in
the RSTATE register indicates that the receiver is stopped.
Generates an interrupt request to the host (if enabled) and sets the GOV bit in the
SCCE.
Stops writing data to all channel’s buffers.
Waits for host to initialize all the receiving channels by setting rst the ZDSTATE
followed by the RSTATE to their initial values.
4.1.3 Restart from a Global Error
The last two bullets in the above two sections describe the only steps necessary for re-
initialization. The transmit and receive sections must be restarted individually for each
separate logical channel.
For details about initialization, see Chapter 6, “QMC Initialization.”
4.2 SCC Event Register (SCCE)
The QMC’s SCCE is a word-length register used to report events and generate interrupt
requests. See Figure 4-2 and Table 4-1 for SCCE eld descriptions. For each of its ags, a
corresponding programmable mask/enable bit in the SCCM determines whether an
interrupt request is generated. If a bit in the SCCM register is zero, the corresponding
interrupt ag does not survive, and the CPM does not proceed with its usual interrupt
handling. If a bit in the SCCM is set, the corresponding interrupt ag in the SCCE survives,
and the SCC event bit is set in the CPM interrupt-pending register. See Figure 4-3 for
SCCM assignments.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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