參數資料
型號： MC68MH360CZQ25L
廠商： Freescale Semiconductor
文件頁數： 106/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 2. QMC Memory Organization
2.4.2.1 CHAMR—Channel Mode Register (Transparent Mode)
The channel mode register is a word-length, host-initialized register. Figure 2-11 shows the
channel mode register for transparent mode.
Notes: 1. All bits dened as reserved are cleared (0).
2. For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-11. CHAMR—Channel Mode Register (Transparent Mode)
Table 2-11 describes the channel mode register’s elds for transparent operation. Boldfaced
parameters must be initialized by the user.
22
TMRBLR
16
Transparent maximum receive buffer length (host-initialized entry)—Denes the
maximum number of bytes written to a receive buffer before moving to the next
buffer for this channel. Note that this value must be a multiple of 4 bytes as the
QMC works on long-word alignment.
24
RSTATE
32
Rx internal state —Initialize to 0x3900
_0000 FC = 9, Motorola mode for MH360,
initialize to 0x3100
_0000 AT = 1, Motorola mode for 860MH. See Section 2.4.2.5,
“RSTATE—Rx Internal State (Transparent Mode),” for more information.
28
32
Rx internal data pointer—Points to current address of specic channel.
2C
RBPTR
16
Rx buffer descriptor pointer (host-initialized to RBASE, prior to operation or due to
a fatal error)—Contains the offset from MCBASE to the current receive buffer. See
Figure 2-2. MCBASE + RBPTR gives the address for the BD in use.
2E
16
Rx internal byte count—Per Channel: Number of remaining bytes in buffer
30
RPACK
32
(Rx temp)—Packs 4 bytes to 1 long word before writing to buffer.
34
ZDSTATE
32
Zero deletion machine state—(Host-initialized to 0x0000
_0080 in HDLC mode,
0x1800
_0080 in transparent mode, prior to operation and after a fatal Rx error
(global overrun, busy) before channel initialization.)—Contains the previous state
of the zero-deletion state machine. The middle 2 bytes, represented by zeros in the
initialization value above, holds the received pattern during reception. A window of
16 bits shows the history of what is received on this logical channel.
38
RES
32
3C
TRNSYNC
16
Transparent synchronization—In transparent mode, this register controls
synchronization for single time slots or superchannel applications. See
Section 2.4.2.4, “TRNSYNC—Transparent Synchronization.”
3E
RES
16
0
123456789
10
11
12
13
14
15
MODE
RD
1
ENT
RES’D
SYNC
RES
POL
0
RESERVED
0
Reset:
0
000000000000000
Table 2-10. Channel-Specific Transparent Parameters (Continued)
Offset
Name
Width
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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