參數(shù)資料
型號: MC68LC302PU20CT
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù): 40/128頁
文件大小: 641K
代理商: MC68LC302PU20CT
MC68EN302 Module Bus Controller
2-2
MC68EN302 REFERENCE MANUAL
MOTOROLA
2.2 TOP LEVEL MEMORY MAP
A top level diagram of register allocation for the modules in the MC68EN302 is shown in
Table 2-1. A description of the DRAM control registers and the Ethernet Controller Registers
are contained in the description of those modules.
Table 2-1. High Level Memory Map of MBC and MB Modules
2.3 MBC REGISTERS
A memory map of the MBC control registers is shown in Table 2-2.
2.4 MODULE BUS CONTROL (MBCTL)
The Module Bus Control register (MBCTL) provides the user control over the system level
functionality of the MBC. This register defaults to $0x5000 upon hardware reset.
BCE—Bus Clear Enable. This bit controls the way in which the MBC responds to the Bus
Clear function inside the MC68EN302. If BCE is zero, the MBC ignores the Bus Clear
(BCLR) signal giving the DRAM and Ethernet modules priority over the 302 core. If this bit
Table 2-2. Module Bus Controller Register Set
ADDRESS
REGISTER NAME
MNEMONIC
MOBA + 000
Module Bus Control Register
MBCTL
MOBA + 002
Interrupt Extension Register
IER
MOBA + 004
Chip Select 0 Extension Register
CSER0
MOBA + 006
Chip Select 1 Extension Register
CSER1
MOBA + 008
Chip Select 2 Extension Register
CSER2
MOBA + 00A
Chip Select 3 Extension Register
CSER3
MOBA + 00C
Parity Control & Status Register
PCSR
15
14
13
12
11
10
9876543210
BCE
MFC2 MFC1 MFC0
BB
PPE
PM9
PM8
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
MOBA + 000
MOBA + 00D
MOBA + 010
MOBA + 019
MOBA + 800
MOBA + FFF
MBC Registers
DRAM Controller Registers
Ethernet Controller Registers
Address
Block
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