參數(shù)資料
型號(hào): MC68HSC05C8FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 143/156頁
文件大小: 1755K
代理商: MC68HSC05C8FB
Serial Peripheral Interface (SPI)
SPI Signal Description
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Serial Peripheral Interface (SPI)
87
10.4.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line one-half cycle before the clock edge (SCK), so the slave
device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI
operation.
Figure 10-1. Data Clock Timing Diagram
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
MSB
6
54321
0
SS
SCK
MISO/MOSI
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