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參數(shù)資料
| 型號： | MC68HSC05C8AP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 49/116頁 |
| 文件大小： | 781K |
| 代理商： | MC68HSC05C8AP |
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Input/Output (I/O) Ports
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
38
Freescale Semiconductor
7.4 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002 and the data direction register
(DDR) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. PC7
has a high current sink and source capability.
7.5 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI subsystem, two more are shared
with the SCI subsystem. Reset does not affect the data registers. During reset, all seven bits become valid
input ports because all special function output drivers associated with the SCI, timer, and SPI subsystems
are disabled.
7.6 Input/Output Programming
I/O port pins may be programmed as inputs or outputs under software control. The direction of the pins is
determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to
a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all I/O pins as inputs. The data direction
registers are capable of being written to or read by the processor. During the programmed output state,
a read of the data register actually reads the value of the output data latch and not the I/O pin. For further
information, refer to Table 7-1 and Figure 7-2.
Table 7-1. I/O Pin Functions
R/W(1)
1. R/W is an internal signal.
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
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