MC68HC05C8A
—
Rev. 3.0
General Release Specification
MOTOROLA
Timer
53
L
G
R
General Release Specification — MC68HC05C8A
Section 8. Timer
8.1 Contents
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Introduction...............................................................................53
Counter.....................................................................................55
Output Compare Register.........................................................56
Input Capture Register..............................................................57
Timer Control Register..............................................................58
Timer Status Register...............................................................60
Timer During Wait Mode...........................................................61
Timer During Stop Mode...........................................................61
8.2 Introduction
The timer consists of a 16-bit, software-programmable counter driven by
a fixed divide-by-four prescaler. This timer can be used for many
purposes, including input waveform measurements while
simultaneously generating an output waveform. Pulse widths can vary
from several microseconds to many seconds. Refer to
Figure 8-1
for a
timer block diagram.
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
NOTE:
The I bit in the condition code register should be set while manipulating
both the high and low byte register of a specific timer function to ensure
that an interrupt does not occur.