參數(shù)資料
型號(hào): MC68HRC705KJ1CS
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CDIP16
封裝: WINDOWED, CERDIP-16
文件頁數(shù): 82/117頁
文件大?。?/td> 1644K
代理商: MC68HRC705KJ1CS
Parallel I/O Ports (PORTS)
Port A
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Parallel I/O Ports (PORTS)
67
Figure 7-4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port
A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch.
When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 7-1 summarizes the operation of the port A pins.
Table 7-1. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
Accesses to Data Bit
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1. Writing affects the data register but does not affect input.
1
Output
Latch
READ DDRA
WRITE DDRA
RESET
WRITE PORTA
READ PORTA
PAx
INTERN
AL
D
AT
A
B
U
S
DDRAx
PAx
PDRAx
SWPDI
100-
A
PULLDOWN
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
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