參數(shù)資料
型號： MC68HRC705KJ1CS
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CDIP16
封裝： WINDOWED, CERDIP-16
文件頁數(shù)： 80/117頁
文件大?。?/td> 1644K
代理商： MC68HRC705KJ1CS
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Parallel I/O Ports (PORTS)
65
Data Sheet — MC68HC705KJ1
Section 7. Parallel I/O Ports (PORTS)
7.1 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port.
All the bidirectional port pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation, termination
reduces excess current consumption and the possibility of electrostatic damage.
Addr.
Register Name:
Bit 7
654321
Bit 0
$0000
Port A Data Register
(PORTA)
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
Unaffected by reset
$0001
Port B Data Register
(PORTB)
Read:
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
$0004
Data Direction Register A
(DDRA)
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
00000000
$0005
Data Direction Register B
(DDRB)
Read:
0
See Note
DDRB3
DDRB2
See Note
Write:
Reset:
00000000
$0010
Port A Pulldown Register
(PDRA)
Read:
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
00000000
$0011
Port B Pulldown Register
(PDRB)
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
000000
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not
available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly
terminating them.
Figure 7-1. Parallel I/O Port Register Summary
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