參數(shù)資料
型號: MC68HRC705KJ1CP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 92/117頁
文件大?。?/td> 1644K
代理商: MC68HRC705KJ1CP
Resets and Interrupts
Data Sheet
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
76
Resets and Interrupts
MOTOROLA
Figure 8-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register enables pins
PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register controls
interrupt triggering sensitivity of external interrupt pins. The IRQ/VPP pin can be
negative-edge triggered only or negative-edge and low-level triggered. Port A
external interrupt pins can be positive-edge triggered only or both positive-edge
and high-level triggered. The level-sensitive triggering option allows multiple
external interrupt sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in Figure 8-5, is latched as long as any source is holding
an external interrupt pin low.
Figure 8-5. External Interrupt Timing
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
IRQ
tILIH
tILIL
tILIH
EXT. INT. PIN
EXT. INT. PIN1
EXT. INT. PINn
.
(INTERNAL)
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