參數(shù)資料
型號： MC68HRC705KJ1CP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 91/117頁
文件大?。?/td> 1644K
代理商： MC68HRC705KJ1CP
Resets and Interrupts
Interrupts
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 4.0
Data Sheet
MOTOROLA
Resets and Interrupts
75
8.2.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part
of a software error detection system and must be cleared periodically to start a new
timeout period. To clear the COP watchdog and prevent a COP reset, write a
logic 0 to bit 0 (COPC) of the COP register at location $07F0.
8.2.4 Illegal Address Reset
An opcode fetch from an address not in RAM or EPROM generates a reset.
8.3 Interrupts
The following sources can generate interrupts:
SWI instruction
External interrupt pins
–IRQ/VPP pin
–
PA0–PA3 pins
Timer
–
Real-time interrupt flag (RTIF)
–
Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a particular event.
An interrupt does not stop the operation of the instruction being executed, but takes
effect when the current instruction completes its execution. Interrupt processing
automatically saves the CPU registers on the stack and loads the program counter
with a user-defined interrupt vector address.
8.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
8.3.2 External Interrupt
An interrupt signal on the IRQ/VPP pin latches an external interrupt request. When
the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is
set, the CPU then tests the I bit in the condition code register. If the I bit is clear,
the CPU then begins the interrupt sequence.
The CPU clears the IRQ latch during interrupt processing, so that another interrupt
signal on the IRQ/VPP pin can latch another interrupt request during the interrupt
service routine. As soon as the I bit is cleared during the return from interrupt, the
CPU can recognize the new interrupt request. Figure 8-4 shows the IRQ/VPP pin
interrupt logic.
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