參數(shù)資料
型號(hào)： MC68HRC705J5ACDWR3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 70/106頁
文件大?。?/td> 1069K
代理商： MC68HRC705J5ACDWR3
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
16-BIT TIMER
MC68HC05J5A
9-8
REV 2.1
Reading the ICH inhibits further captures until the ICL is also read. Reading the
ICL after reading the timer status register (T1SR) clears the ICF ag bit. does not
inhibit transfer of the free-running counter. There is no conict between reading
the ICL and transfers from the free-running timer counters. The input capture reg-
isters always contain the free-running timer counter value which corresponds to
the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICH and ICL, set the
I bit in the condition code register (CCR) before reading ICH and clear the I bit
after reading ICL.
9.4
TIMER1 CONTROL REGISTER (T1CR)
The timer control register is shown in Figure 9-11 performs the following func-
tions:
Enables input capture interrupts
Enables output compare interrupts
Enables timer overow interrupts
Control the active edge polarity of the TCAP signal on pin PB0/TCAP
Reset clears all the bits in the T1CR with the exception of the IEDG bit which is
unaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB0/
TCAP pin. Reset clears the ICIE bit.
1 =
Input capture interrupts enabled.
0 =
Input capture interrupts disabled.
T1OIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer1 overow. Reset clears
the T1OIE bit.
1 =
Timer1 overow interrupts enabled.
0 =
Timer1 overow interrupts disabled.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T1CR
R
ICIE
0
T1OIE
000
IEDG
0
$0012
W
reset:
000000
U
0
U = UNAFFECTED BY RESET
Figure 9-11. Timer Control Register (T1CR)
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