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參數(shù)資料
| 型號(hào)： | MC68HLC908QY2CDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 64/186頁(yè) |
| 文件大?。?/td> | 2765K |
| 代理商： | MC68HLC908QY2CDT |
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Development Support
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
156
Development Support
MOTOROLA
Simple monitor commands can access any memory address. In monitor mode, the
MCU can execute code downloaded into RAM by a host computer while most MCU
pins retain normal operating mode functions. All communication between the host
computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing
interface is required between PTA0 and the host computer. PTA0 is used in a
wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to
allow enabling the internal oscillator to generate the internal clock. This addition,
which is enabled when IRQ is held low out of reset, is intended to support serial
communication/programming at 4800 baud in monitor mode by using the internal
oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location
$FFC0, if programmed) to generate the desired internal frequency (1.0 MHz).
Since this feature is enabled only when IRQ is held low out of reset, it cannot be
used when the reset vector is programmed (i.e., the value is not $FFFF) because
entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the
table, monitor mode may be entered after a power-on reset (POR) and will allow
communication at 9600 baud provided one of the following sets of conditions is
met:
If $FFFE and $FFFF do not contain $FF (programmed state):
–
The external clock is 9.8304 MHz
–IRQ = VTST
If $FFFE and $FFFF contain $FF (erased state):
–
The external clock is 9.8304 MHz
–IRQ = VDD (this can be implemented through the internal IRQ pullup)
If $FFFE and $FFFF contain $FF (erased state):
–IRQ = VSS (internal oscillator is selected, no external clock required)
The rising edge of the internal RST signal latches the monitor mode. Once monitor
mode is latched, the values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see
15.3.2 Security). After the security bytes, the MCU sends a break signal (10
consecutive logic 0s) to the host, indicating that it is ready to receive a command.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HLC908QY2CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/ADC - Bulk |
| MC68HLC908QY2CP | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/ADC - Bulk |
| MC68HLC908QY2DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QY4CDW | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HLC908QY4CP | 制造商:Rochester Electronics LLC 功能描述:LOW V-4K FLASH W/ADC - Bulk |
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