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| 型號(hào)： | MC68HLC908QT4CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁(yè)數(shù)： | 138/186頁(yè) |
| 文件大小： | 2583K |
| 代理商： | MC68HLC908QT4CDW |
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Configuration Register (CONFIG)
Functional Description
MC68HLC908QY/QT Family — Rev. 2
Data Sheet
MOTOROLA
Configuration Register (CONFIG)
55
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. Unlike other
configuration bits, the LVIRSTD can be written at any time.
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit
LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used
as a low voltage warning, while LVR will commonly be used as a reset condition.
Unlike other CONFIG bits, LVDLVR can be written multiple times after reset.
1 = LVI trip voltage level set to LVD trip voltage
0 = LVI trip voltage level set to LVR trip voltage
NOTE:
The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets will leave
this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4
cycles instead of a 4096 BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE:
Exiting stop mode by an LVI reset will result in the long stop recovery.
When using the LVI during normal operation but disabling during stop mode, the
LVI will have an enable time of tEN. The system stabilization time for power-on
reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay
longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when
using the short stop recovery configuration option, the 32 BUSCLKX4 delay
must be greater than the LVI’s turn on time to avoid a period in startup where
the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HLC908QY4CDW | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MC68HLC908QY2DW | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MC68HLC908QY2CDT | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| MC68HLC908QY2CP | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDIP16 |
| MC68HLC908QT4P | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HLC908QT4CFQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QY1CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/O ADC - Bulk |
| MC68HLC908QY1DT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC68HLC908QY2CDT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HLC908QY2CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/ADC - Bulk |
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