Memory
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
32
Memory
MOTOROLA
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. The
FLASH memory can be read, programmed, and erased from a single external
supply. The program and erase operations are enabled through the use of an
internal charge pump.
The FLASH memory consists of an array of 4096 or 1536 bytes with an additional
48 bytes for user vectors. The minimum size of FLASH memory that can be erased
is 64 bytes; and the maximum size of FLASH memory that can be programmed in
a program cycle is 32 bytes (a row). Program and erase operations are facilitated
through control bits in the FLASH control register (FLCR). Details for these
operations appear later in this section. The address ranges for the user memory
and vectors are:
$EE00 – $FDFF; user memory, 4096 bytes: MC68HLC908QY4 and
MC68HLC908QT4
$F800 – $FDFF; user memory, 1536 bytes: MC68HLC908QY2,
MC68HLC908QT2, MC68HLC908QY1 and MC68HLC908QT1
$FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE:
An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature
prevents viewing of the FLASH contents.(1)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory
for either program or erase operation. It can only be set if either PGM =1 or
ERASE =1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
Address:
$FE08
Bit 7
654321
Bit 0
Read:
0000
HVEN
MASS
ERASE
PGM
Write:
Reset:
00000000
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)