參數(shù)資料
型號(hào)： MC68HCP11A1VP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 16/158頁
文件大小： 3803K
代理商： MC68HCP11A1VP2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
10-14
TECHNICAL DATA
10
2-11
PULY
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
1
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($38)
Irrelevant Data
IYH (High Byte) from Stack
IYH (Low Byte) from Stack
2-12
RTS
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer +1
Stack Pointer + 2
1
Opcode ($39)
Irrelevant Data
Address of Next Instruction
(High Byte)
Address of Next Instruction
(Low Byte)
2-13
MUL
10
1
2
3
4
5
6
7
8
9
10
Opcode Address
Opcode Address + 1
$FFFF
1
Opcode ($3D)
Irrelevant Data
2-14
RTI
12
1
2
3
4
5
6
7
8
9
10
11
12
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Stack Pointer + 8
Stack Pointer + 9
1
Opcode ($3B)
Irrelevant Data
Condition Code Register from
Stack
B Accumulator from Stack
A Accumulator from Stack
IXH (High Byte) from Stack
IXL (Low Byte) from Stack
IYH (High Byte) from Stack
IYL (Low Byte) from Stack
Address of Next Instruction
(High Byte)
Address of Next Instruction
(Low Byte)
2-15
SWI
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer – 1
Stack Pointer – 2
Stack Pointer – 3
Stack Pointer – 4
Stack Pointer – 5
Stack Pointer – 6
Stack Pointer – 7
Stack Pointer – 8
Address of SWI
Vector (First Location)
Address of Vector + 1
(Second Location)
1
0
1
Opcode ($3F)
Irrelevant Data
Return Address (Low Byte)
Return Address (High Byte)
IYL (Low Byte) to Stack
IYH (High Byte) to Stack
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
A Accumulator to Stack
B Accumulator to Stack
Condition Code Register to
Stack
Irrelevant Data
SWI Service Routine Address
(High Byte)
SWI Service Routine Address
(Low Byte)
Table 10-2 Cycle-by-Cycle Operation — Inherent Mode (Sheet 2 of 4)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
* The reference number is given to provide a cross-reference to Table 10-1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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