參數(shù)資料
型號： MC68HCP11A1VP2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 12/158頁
文件大?。?/td> 3803K
代理商： MC68HCP11A1VP2
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-11
10
**Infinity or Until Reset Occurs
***12 Cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer
number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch
the appropriate interrupt vector (14 + n total).
dd
= 8-Bit Direct Address ($0000 –$00FF) (High Byte Assumed to be $00)
ff
= 8-Bit Positive Offset $00 (0) to $FF (255) (Is Added to Index)
hh
= High Order Byte of 16-Bit Extended Address
ii
= One Byte of Immediate Data
jj
= High Order Byte of 16-Bit Immediate Data
kk
= Low Order Byte of 16-Bit Immediate Data
ll
= Low Order Byte of 16-Bit Extended Address
mm
= 8-Bit Bit Mask (Set Bits to be Affected)
rr
= Signed Relative Offset $80 (– 128) to $7F (+ 127)
(Offset Relative to the Address Following the Machine Code Offset Byte)
TEST
TEST (Only in Test Modes)
Address Bus Counts
INH
00
1
**
2-20
- - - - - - - -
TPA
Transfer CC Register to A
CCR
→ A
INH
07
1
2
2-1
- - - - - - - -
TST (opr)
Test for Zero or Minus
M – 0
EXT
IND,X
IND,Y
7D
6D
18 6D
hh
ll
ff
3
2
3
6
7
5-9
6-4
7-4
- - - - ¤ ¤ 0 0
TSTA
A – 0
A INH
4D
1
2
2-1
- - - - ¤ ¤ 0 0
TSTB
B – 0
B INH
5D
1
2
2-1
- - - - ¤ ¤ 0 0
TSX
Transfer Stack Pointer to X
SP + 1
→ IX
INH
30
1
3
2-3
- - - - - - - -
TSY
Transfer Stack Pointer to Y
SP + 1
→ IY
INH
18 30
2
4
2-5
- - - - - - - -
TXS
Transfer X to Stack Pointer
IX – 1
→ SP
INH
35
1
3
2-2
- - - - - - - -
TYS
Transfer Y to Stack Pointer
IY – 1
→ SP
INH
18 35
2
4
2-4
- - - - - - - -
WAI
Wait for Interrupt
Stack Regs & WAlT
INH
3E
1
***
2-16
- - - - - - - -
XGDX
Exchange D with X
IX
→ D, D → IX
INH
8F
1
3
2-2
- - - - - - - -
XGDY
Exchange D with Y
IY
→ D, D → IY
INH
18 8F
2
4
2-4
- - - - - - - -
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 6 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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