參數(shù)資料
型號(hào): MC68HCP11A1MP2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PDIP48
封裝: DIP-48
文件頁數(shù): 113/158頁
文件大?。?/td> 776K
代理商: MC68HCP11A1MP2
MC68HC11A8
TECHNICAL DATA
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
10-15
10
2-16
WAI
14 + n
1
2
3
4
5
6
7
8
9
10
11
12 to
n + 12
n + 13
n + 14
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer – 1
Stack Pointer – 2
Stack Pointer – 3
Stack Pointer – 4
Stack Pointer – 5
Stack Pointer – 6
Stack Pointer – 7
Stack Pointer – 8
Stack Pointer – 8
Address of Vector
(First Location)
Address of Vector + 1
(Second Location)
Opcode Address
Opcode Address + 1
$FFFF
Opcode Address
Opcode Address + 1
$FFFF
Stack Pointer
Stack Pointer – 1
Stack Pointer – 2
Stack Pointer – 3
Stack Pointer – 4
Stack Pointer – 5
Stack Pointer – 6
Stack Pointer – 7
Stack Pointer – 8
1
1
0
0
0
0
0
0
0
0
0
1
1
1
Opcode ($3E)
Irrelevant Data
Return Address (Low Byte)
Return Address (High Byte)
IYL (Low Byte) to Stack
IYH (High Byte) to Stack
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
A Accumulator to Stack
B Accumulator to Stack
Condition Code Register to
Stack
Irrelevant Data
Service Routine Address (High
Byte)
Service Routine Address (Low
Byte)
Opcode
Irrelevant Data
Irrelevant Data
Opcode (Illegal)
Irrelevant Data
Irrelevant Data
Return Address (Low Byte)
Return Address (High Byte)
IYL (Low Byte) to Stack
IYH (High Byte) to Stack
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
A Accumulator
B Accumulator
Condition Code Register to
Stack
Irrelevant Data
Service Routine Address
(High Byte)
Service Routine Address
(Low Byte)
Opcode (Legal Page Select)
Opcode (Illegal Second Byte)
Irrelevant Data
Irrelevant Data
Return Address (Low Byte)
Return Address (High Byte)
IYL (Low Byte) to Stack
IYH (High Byte) to Stack
IXL (Low Byte) to Stack
IXH (High Byte) to Stack
A Accumulator
B Accumulator
Condition Code Register to
Stack
Irrelevant Data
Service Routine Address
(High Byte)
Service Routine Address
(Low Byte)
2-17
FDIV, IDIV
41
1
2
3 – 41
1
2
3
4
5
6
7
8
9
10
11
12
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
2-18
Page 1 Illegal
Opcodes
15
13
14
15
Stack Pointer – 8
Address of Vector
(First Location)
Address of Vector + 1
(Second Location)
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
Stack Pointer
Stack Pointer – 1
Stack Pointer – 2
Stack Pointer – 3
Stack Pointer – 4
Stack Pointer – 5
Stack Pointer – 6
Stack Pointer – 7
Stack Pointer – 8
1
1
1
2-19
Pages 2, 3, or 4
Illegal Opcodes
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Stack Pointer – 8
Address of Vector
(First Location)
Address of Vector + 1
(Second Location)
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
Table 10-2 Cycle-by-Cycle Operation — Inherent Mode (Sheet 3 of 4)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
* The reference number is given to provide a cross-reference to Table 10-1.
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