參數(shù)資料
型號: MC68HCP11A1MP2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PDIP48
封裝: DIP-48
文件頁數(shù): 106/158頁
文件大?。?/td> 776K
代理商: MC68HCP11A1MP2
MOTOROLA
10-8
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
CPX (opr)
Compare X to Memory 16-Bit
IX – M:M + 1
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
EXT
IND,X
IND,Y
A INH
B INH
INH
INH
INH
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
INH
INH
EXT
IND,X
IND,Y
A INH
B INH
INH
INH
INH
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
IMM
DIR
EXT
IND,X
IND,Y
8C
9C
BC
AC
CD AC
18 8C
18 9C
18 BC
1A AC
18 AC
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
3
2
3
2
3
4
3
4
3
3
1
3
2
3
1
1
1
1
2
2
2
3
2
3
2
2
3
2
3
1
1
3
2
3
1
1
1
1
2
3
2
3
2
3
2
3
2
2
3
2
3
2
2
3
2
3
3
2
3
2
3
4
5
6
6
7
5
6
7
7
7
2
6
6
7
2
2
3
3
4
2
3
4
4
5
2
3
4
4
5
41
41
6
6
7
2
2
3
3
4
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3-3
4-7
5-10
6-10
7-8
3-5
4-9
5-11
6-11
7-8
2-1
5-8
6-3
7-3
2-1
2-1
2-3
2-2
2-4
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
2-17
2-17
5-8
6-3
7-3
2-1
2-1
2-3
2-2
2-4
5-1
6-1
7-1
4-8
5-12
6-12
7-9
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
3-2
4-3
5-4
6-6
7-6
- - - -
¤ ¤ ¤ ¤
CPY (opr)
Compare Y to Memory
16-Bit
IY – M:M + 1
- - - -
¤ ¤ ¤ ¤
DAA
DEC (opr)
Decimal Adjust A
Decrement Memory Byte
Adjust Sum to BCD
M – 1
M
19
7A
6A
- - - -
¤ ¤ ¤ ¤
- - - -
¤ ¤ ¤
-
18 6A
hh ll
ff
ff
DECA
DECB
DES
DEX
DEY
EORA (opr) Exclusive OR A with Memory
Decrement Accumulator A
Decrement Accumulator B
Decrement Stack Pointer
Decrement Index Register X
Decrement Index Register Y
A – 1
A
B – 1
B
SP – 1
SP
IX – 1
IX
IY – 1
IY
A
M
A
4A
5A
34
09
- - - -
¤ ¤ ¤
-
- - - -
¤ ¤ ¤
-
- - - - - - - -
- - - - -
¤
- -
- - - - -
¤
- -
- - - -
¤ ¤
0 -
18 09
88
98
88
A8
18 A8
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
EORB (opr) Exclusive OR B with Memory
B
M
B
C8
D8
F8
E8
18 E8
- - - -
¤ ¤
0 -
FDIV
IDIV
INC (opr)
Fractional Divide 16 by 16
Integer Divide 16 by 16
Increment Memory Byte
D/IX
IX; r
D
D/IX
IX; r
D
M + 1
M
03
02
7C
6C
- - - - -
¤ ¤ ¤
- - - - -
¤
0
¤
- - - -
¤ ¤ ¤
-
18 6C
hh ll
ff
ff
INCA
INCB
INS
INX
INY
JMP (opr)
Increment Accumulator A
Increment Accumulator B
Increment Stack Pointer
Increment Index Register X
Increment Index Register Y
Jump
A + 1
A
B + 1
B
SP + 1
SP
IX + 1
IX
IY + 1
IY
See Special Ops
4C
5C
31
08
- - - -
¤ ¤ ¤
-
- - - -
¤ ¤ ¤
-
- - - - - - - -
- - - - -
¤
- -
- - - - -
¤
- -
- - - - - - - -
18 08
7E
6E
18 6E
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
JSR (opr)
Jump to Subroutine
See Special Ops
9D
BD
AD
18 AD
- - - - - - - -
LDAA (opr) Load Accumulator A
M
A
86
96
B6
A6
18 A6
- - - -
¤ ¤
0 -
LDAB (opr) Load Accumulator B
M
B
C6
D6
F6
E6
18 E6
CC
DC
FC
EC
18 EC
- - - -
¤ ¤
0 -
LDD (opr)
Load Double Accumulator D
M
A,M + 1
B
- - - -
¤ ¤
0 -
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 3 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Opcode
B
C
Cycle
by
Cycle*
Condition Codes
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
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