參數(shù)資料
型號(hào)： MC68HCL05P1ADW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 96/124頁
文件大?。?/td> 3724K
代理商： MC68HCL05P1ADW
16-Bit Timer
Timer Control Register
MC68HC05P1A — Rev. 3.0
General Release Specification
16-Bit Timer
NON-DISCLOSURE
AGREEMENT
REQUIRED
8.6 Timer Control Register
The timer control (TCR) and free-running counter (TMRH, TMRL,
ACRH, and ACRL) registers are the only registers of the 16-bit timer
affected by reset. The output compare port (TCMP) is forced low after
reset and remains low until OLVL is set and a valid output compare
occurs.
ICIE — Input Capture Interrupt Enable
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
OCIE — Output Compare Interrupt Enable
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
TOIE — Timer Overflow Interrupt Enable
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
IEDG — Input Capture Edge Select
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge;
setting it selects the rising edge.
OLVL — Output Compare Output Level Select
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
$0012
Bit 7
654321
Bit 0
Read:
ICIE
OCIE
TOIE
000
IEDG
OLVL
Write:
Reset:
000000
U
0
U = Unaffected
Figure 8-11. Timer Control Register (TCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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