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參數(shù)資料
| 型號： | MC68HCL05C8AFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 69/116頁 |
| 文件大?。?/td> | 781K |
| 代理商： | MC68HCL05C8AFN |
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Serial Communications Interface (SCI)
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
56
Freescale Semiconductor
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set, and no data, preamble, or break character
is being transmitted. TC generates an interrupt request if the TCIE bit in SCCR2 is also set. Clear the
TC bit by reading the SCSR with TC set, and then writing to the SCDR. Reset sets the TC bit. Software
must initialize the TC bit to logic 0 to avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. RDRF generates an interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF bit
by reading the SCSR with RDRF set, and then reading the SCDR. Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an interrupt request if the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading
the SCSR with IDLE set, and then reading the SCDR. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun Bit
This clearable, read-only bit is set if the SCDR is not read before the receive shift register receives the
next word. OR generates an interrupt request if the RIE bit in SCCR2 is also set. The data in the shift
register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading the SCSR
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data received in the SCI data register.
Clear the NF bit by reading the SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a stop bit should be in the character
shifted into the receive shift register. If the received word causes both a framing error and an overrun
error, the OR bit is set and the FE bit is not set. Clear the FE bit by reading the SCSR, and then reading
the SCDR. Reset clears the FE bit.
1 = Framing error
0 = No framing error
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相關(guān)代理商/技術(shù)參數(shù) |
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