參數(shù)資料
型號(hào)： MC68HCL05C8AFN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 56/116頁
文件大?。?/td> 781K
代理商： MC68HCL05C8AFN
Timer
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
44
Freescale Semiconductor
8.4 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch
the value of the free-running counter after the corresponding input capture edge detector senses a
defined transition. The level transition which triggers the counter transfer is defined by the corresponding
input edge bit (IEDG). Reset does not affect the contents of the input capture register except when exiting
stop mode.
The result obtained by an input capture will be one more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter, which is four internal bus clock
cycles.
The free-running counter contents are transferred to the input capture register on each proper signal
transition regardless of whether the input capture flag (ICF) is set or clear. The input capture register
always contains the free-running counter value that corresponds to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter transfer, since they
occur on opposite edges of the internal bus clock. Figure 8-3 shows the logic of the input capture function.
Figure 8-3. Input Capture Operation
INPUT CAPTURE REGISTER HIGH
INPUT CAPTURE REGISTER LOW
TIMER REGISTER HIGH
TCMP
EDGE
SELECT/DETECT
LOGIC
TIMER
INTERRUPT
REQUEST
TIMER REGISTER LOW
15
0
15
8 7
0
TIMER STATUS REGISTER
$0013
TIMER CONTROL REGISTER
$0012
ICI
E
OCIE
TO
IE
ICF
OCF
TO
F
87
$0018
$0019
$0014
$0015
IEDG
LATCH
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