參數(shù)資料
型號： MC68HCL05C8AB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SHRINK, PLASTIC, DIP-42
文件頁數(shù)： 137/166頁
文件大?。?/td> 1914K
代理商： MC68HCL05C8AB
Serial Communications Interface (SCI)
Technical Data
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
72
Serial Communications Interface (SCI)
MOTOROLA
9.5.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to
the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register.
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then
writing data to the SCDR begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
When the shift register is not transmitting a character, the PD1/TDO pin
goes to the idle condition, logic 1. If software clears the TE bit during the
idle condition, and while TDRE is set, the transmitter relinquishes control
of the PD1/TDO pin.
9.5.1.3 Break Characters
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
K bit in SCCR2 loads the shift register with a
break character. A break character contains all logic 0s and has no start
and stop bits. Break character length depends on the M bit in SCCR1.
As long as SBK is at logic 1, transmitter logic continuously loads break
characters into the shift register. After software clears the SBK bit, the
shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break
character is to guarantee the recognition of the start bit of the next
character.
相關(guān)PDF資料
PDF描述
MC68HSC05C8CFB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
MC68HC05C8AMB 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HSC05C8AB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
MC68HC05C8CFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
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