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| 型號(hào)： | MC68HC908QY8VPE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 32 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | LEAD FREE, PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 88/236頁(yè) |
| 文件大?。?/td> | 2921K |
| 代理商： | MC68HC908QY8VPE |
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Timer Interface Module (TIM)
MC68HC908QB8 Data Sheet, Rev. 2
178
Freescale Semiconductor
channel, the TIM can set, clear, or toggle the channel pin. Output compares can be enabled to generate
interrupt requests.
16.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 16.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
16.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
TCH2 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2) links channel 2 and channel 3.
The output compare value in the TIM channel 2 registers initially controls the output on the TCH2 pin.
Writing to the TIM channel 3 registers enables the TIM channel 3 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (2 or 3) that
control the output are the ones written to last. TSC2 controls and monitors the buffered output compare
function, and TIM channel 3 status and control register (TSC3) is unused. While the MS2B bit is set, the
channel 3 pin, TCH3, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
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