參數(shù)資料
型號(hào)： MC68HC901
廠商： Motorola, Inc.
英文描述： Multi-Function Peripheral
中文描述： 多功能外設(shè)
文件頁(yè)數(shù)： 22/73頁(yè)
文件大小： 274K
代理商： MC68HC901
Bus Operation
MOTOROLA
MC68HC901 USER’S MANUAL
3-3
When the MFP asserts DTACK to indicate that valid data is on the bus, the processor will
latch the data and terminate the bus cycle by negating DS. When either DS or IACK is
negated, the MFP will terminate the interrupt acknowledge operation by driving DTACK high
and placing it in the high-impedance state. IRQ will be negated as a result of the IACK cycle
unless additional interrupts are pending.
The MFP can be part of a daisy-chain interrupt structure which allows multiple MFPs to be
placed at the same interrupt level by sharing a common IACK signal. A daisy-chain priority
scheme is implemented with signals IEI and IEO. IEI indicates that no higher priority device
is requesting interrupt service. IEO signals lower priority devices that neither this device nor
any higher priority MFP is requesting service. To daisy-chain MFPs, the highest priority MFP
has its IEI tied low and successive MFPs have their IEI connected to the next higher priority
MFPs IEO. When the daisy-chain interrupt structure is not implemented, the IEIs of all MFPs
must be tied low and the IEOs left unconnected. Refer to
MFPs
for additional information.
Section 4.2 Daisy-Chaining
When the processor initiates an interrupt acknowledge cycle by driving IACK and DS, the
MFP, whose IEI is low, may respond with a vector number if an interrupt is pending. If this
device does not have a pending interrupt, IEO is asserted which allows the next lower
priority device to respond to the interrupt acknowledge. When an MFP propagates IEO, it
will not drive the data bus nor DTACK during the interrupt acknowledge cycle. The timing for
an IACK cycle is shown in Figure 3-3. Refer to
and Figures 7-7 and 7-8 for further information.
Section 8.7 AC Electrical Characteristics
Figure 3-3. IACK Cycle Timing Diagram
3.3 RESET OPERATION
The reset operation will initialize the MFP to a known state. The reset operation requires that
the RESET input be asserted for a minimum of two microseconds. During a device reset
condition, all internal MFP registers are cleared except for the timer data registers (TADR,
TBDR, TCDR, and TDDR), the USART data register (UDR), and the transmitter status
register (TSR). All timers are stopped, the USART receiver and transmitter are disabled, and
the serial output (SO) line is placed in high impedance. The interrupt channels are also
disabled and any pending interrupts are cleared. In addition, the general purpose interrupt
CLK
D0 - D7
DTACK
DS
IACK
IEI
IEO
MC68HC901UM / AD
FIGURE - IACK CYCLE TIMING DIAGRAM
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