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參數(shù)資料
| 型號： | MC68HC711K4CFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 47/80頁 |
| 文件大?。?/td> | 420K |
| 代理商： | MC68HC711K4CFN2 |
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M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
47
NOTE
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to
4.3 Memory
Expansion and Chip Selects
and
12 Pulse-Width Modulation Timer
for further
information.
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
DDG[7:0] —Data Direction for Port G
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
Bits [7:6] —Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
NOTE
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to
4.1 Memory Ex-
pansion
for further information.
PORTG
—Port G Data
$007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
DDRG
—Data Direction Register for Port G
$007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
RESET:
0
0
0
0
0
0
0
0
PGAR
—
Port G Assignment
$002D
Bit 7
6
5
4
3
2
1
Bit 0
$
0
02D
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
RESET:
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC11K4CFN2 | Technical Summary 8-Bit Microcontroller |
| MC68HC11K4CFN3 | Technical Summary 8-Bit Microcontroller |
| MC68HC11K1VFU2 | 8-BIT MICROCONTROLLER |
| MC68HC11K4VFU2 | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:3"; External Depth:3.9" |
| MC68HC11K1VFU3 | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:10"; External Width:7.1"; External Depth:2.5"; Enclosure Color:Light Gray; Approval Bodies:UL, CSA; Cover Color:Light Gray RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC711K4CFN4 | 功能描述:IC MCU 24K OTP 4MHZ 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC711K4CFNE3 | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC711K4CFNE4 | 制造商:Freescale Semiconductor 功能描述: |
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| MC68HC711KS2CPU4 | 制造商:Motorola Inc 功能描述: |
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