Central Processor Unit (CPU)
Instruction Set
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
87
SWI
Software
Interrupt
Transfer A to B
Transfer A to
CC Register
Transfer B to A
TEST (Only in
Test Modes)
Transfer CC
Register to A
Test for Zero or
Minus
See Figure 3–2
INH
3F
—
14
—
—
—
1
—
—
—
—
TAB
TAP
A
B
A
CCR
INH
INH
16
06
—
—
2
2
—
—
↓
—
—
0
—
TBA
TEST
B
A
INH
INH
17
00
—
—
2
*
—
—
—
—
—
—
—
—
—
—
0
—
—
—
Address Bus Counts
TPA
CCR
A
INH
07
—
2
—
—
—
—
—
—
—
—
TST (opr)
M – 0
EXT
IND,X
IND,Y
INH
7D
6D
6D
4D
18
hh ll
ff
ff
6
6
7
2
—
—
—
—
0
0
TSTA
Test A for Zero
or Minus
Test B for Zero
or Minus
Transfer Stack
Pointer to X
Transfer Stack
Pointer to Y
Transfer X to
Stack Pointer
Transfer Y to
Stack Pointer
Wait for
Interrupt
Exchange D
with X
Exchange D
with Y
A – 0
A
—
—
—
—
—
0
0
TSTB
B – 0
B
INH
5D
—
2
—
—
—
—
0
0
TSX
SP + 1
IX
INH
30
—
3
—
—
—
—
—
—
—
—
TSY
SP + 1
IY
INH
18
30
—
4
—
—
—
—
—
—
—
—
TXS
IX – 1
SP
INH
35
—
3
—
—
—
—
—
—
—
—
TYS
IY – 1
SP
INH
18
35
—
4
—
—
—
—
—
—
—
—
WAI
Stack Regs & WAIT
INH
3E
—
**
—
—
—
—
—
—
—
—
XGDX
IX
D, D
IX
INH
8F
—
3
—
—
—
—
—
—
—
—
XGDY
IY
D, D
IY
INH
18
8F
—
4
—
—
—
—
—
—
—
—
Table 4-2. Instruction Set (Sheet 7 of 7)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
Cycle
*
**
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
Operands
dd
ff
hh
ii
jj
kk
ll
mm
rr
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
= High-order byte of 16-bit extended address
= One byte of immediate data
= High-order byte of 16-bit immediate data
= Low-order byte of 16-bit immediate data
= Low-order byte of 16-bit extended address
= 8-bit mask (set bits to be affected)
= Signed relative offset $80 (–128) to $7F (+127)
(offset relative to address following machine code offset byte))
Operators
( )
+
Contents of register shown inside parentheses
Is transferred to
Is pulled from stack
Is pushed onto stack
Boolean AND
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction symbol or negation symbol (two’s complement)
⊕
:
–
Condition Codes
—
0
1
↓
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
F
Freescale Semiconductor, Inc.
n
.