- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69028 > MC68HC711D3MP2 (MOTOROLA INC) 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40 PDF資料下載
參數(shù)資料
| 型號： | MC68HC711D3MP2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 149/157頁 |
| 文件大小： | 2252K |
| 代理商： | MC68HC711D3MP2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁當(dāng)前第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
Serial Peripheral Interface (SPI)
SPI System Errors
MC68HC711D3 — Rev. 2
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI)
91
The state of the master and slave CPHA bits affects the operation of SS. CPHA
settings should be identical for master and slave. When CPHA = 0, the shift clock
is the OR of SS with SCK. In this clock phase mode, SS must go high between
successive characters in an SPI message. When CPHA = 1, SS can be left low
between successive SPI characters. In cases where there is only one SPI slave
MCU, its SS line can be tied to VSS as long as only CPHA = 1 clock mode is used.
7.6 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises
in a multiple-master system when more than one SPI device simultaneously tries
to be a master. This error is called a mode fault. The second type of error, write
collision, indicates that an attempt was made to write data to the SPDR while a
transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active
low, a mode fault error has occurred — usually because two devices have
attempted to act as master at the same time. In cases where more than one device
is concurrently configured as a master, there is a chance of contention between
two pin drivers. For push-pull CMOS drivers, this contention can cause permanent
damage. The mode fault attempts to protect the device by disabling the drivers.
The MSTR control bit in the SPCR and all four DDRD control bits associated with
the SPI are cleared. An interrupt is generated subject to masking by the SPIE
control bit and the I bit in the CCR.
Other precautions may need to be taken to prevent driver damage. If two devices
are made masters at the same time, mode fault does not help protect either one
unless one of them selects the other as slave. The amount of damage possible
depends on the length of time both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress.
Because the SPDR is not double buffered in the transmit direction, writes to SPDR
cause data to be written directly into the SPI shift register. Because this write
corrupts any transfer in progress, a write collision error is generated. The transfer
continues undisturbed, and the write data that caused the error is not written to the
shifter.
A write collision is normally a slave error because a slave has no control over when
a master initiates a transfer. A master knows when a transfer is in progress, so
there is no reason for a master to generate a write-collision error, although the SPI
logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For
a master, a transfer begins when data is written to SPDR and ends when SPIF is
set. For a slave with CPHA equal to zero, a transfer starts when SS goes low and
ends when SS returns high. In this case, SPIF is set at the middle of the eighth SCK
cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to one,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC711D3S | 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP40 |
| MC68HC711D3FN | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC711G5CFN | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11G7CFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC711L6CFN1 | OTPROM, MICROCONTROLLER, PQCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC711D3VFNE2 | 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC711E20CFN2 | 功能描述:IC MCU 20K 2MHZ OTP 52-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC711E20CFN3 | 功能描述:IC MCU 3MHZ 20K OTP 52-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC711E20CFN4 | 功能描述:IC MCU 20K OTP 4MHZ 52-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC711E20CFU3 | 制造商:Rochester Electronics LLC 功能描述:8BIT, 20K EPROM, 768RAM. - Bulk 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。