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    參數(shù)資料
    型號: MC68HC711D3CFN1
    廠商: MOTOROLA INC
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, OTPROM, MICROCONTROLLER, PQCC44
    封裝: PLASTIC, LCC-44
    文件頁數(shù): 19/131頁
    文件大?。?/td> 1640K
    代理商: MC68HC711D3CFN1
    MC68HC11D3
    ELECTRICAL CHARACTERISTICS
    MOTOROLA
    TECHNICAL DATA
    A-11
    NOTES:
    1. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
    2. Signal production depends on software.
    3. Assumes 100 pF load on all SPI pins.
    Table A-7 Serial Peripheral Interface Timing
    Num
    Characteristic
    Symbol
    2.0 MHz
    3.0 MHz
    Unit
    Min
    Max
    Min
    Max
    Operating Frequency
    Master
    Slave
    fop(m)
    fop(s)
    dc
    0.5
    2.0
    dc
    0.5
    3.0
    fop
    MHz
    1
    Cycle Time
    Master
    Slave
    tcyc(m)
    tcyc(s)
    2.0
    500
    2.0
    333
    tcyc
    ns
    2
    Enable Lead Time
    Master (Note 2)
    Slave
    tlead(m)
    tlead(s)
    250
    240
    ns
    3
    Enable Lag Time
    Master (Note 2)
    Slave
    tlag(m)
    tlag(s)
    250
    240
    ns
    4
    Clock (SCK) High Time
    Master
    Slave
    tw(SCKH)m
    tw(SCKH)s
    340
    190
    340
    190
    ns
    5
    Clock (SCK) Low Time
    Master
    Slave
    tw(SCKL)m
    tw(SCKL)s
    340
    190
    340
    190
    ns
    6
    Data Setup Time (Inputs)
    Master
    Slave
    tsu(m)
    tsu(s)
    100
    100
    ns
    7
    Data Hold Time (Inputs)
    Master
    Slave
    th(m)
    th(s)
    100
    100
    ns
    8
    Access Time
    (Time to Data Active from High-Imp. State)
    Slave
    ta
    0
    120
    0
    120
    ns
    9
    Disable Time
    (Hold Time to High-Impedance State)
    Slave
    tdis
    240
    167
    ns
    10
    Data Valid (After Enable Edge) (Note 3)
    tv(s)
    240
    167
    ns
    11
    Data Hold Time (Outputs) (After Enable Edge)
    tho
    0—
    ns
    12
    Rise Time (20% VDD to 70% VDD, CL = 200 pF)
    SPI Outputs (SCK, MOSI, and MISO)
    SPI Inputs (SCK, MOSI, MISO, and SS)
    trm
    trs
    100
    2.0
    100
    2.0
    ns
    s
    13
    Fall Time (70% VDD to 20% VDD, CL = 200 pF)
    SPI Outputs (SCK, MOSI, and MISO)
    SPI Inputs (SCK, MOSI, MISO, and SS)
    tfm
    tfs
    100
    2.0
    100
    2.0
    ns
    s
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