參數(shù)資料
型號： MC68HC711D3CFN1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 17/131頁
文件大?。?/td> 1640K
代理商： MC68HC711D3CFN1
MC68HC11D3
ELECTRICAL CHARACTERISTICS
MOTOROLA
TECHNICAL DATA
A-9
NOTES:
1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock
duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following
expressions in place of 1/8 tcyc in the above formulas, where applicable:
(a) (1-DC)
× 1/4 t
cyc
(b) DC
× 1/4 t
cyc
Where:
DC is the decimal value of duty cycle percentage (high time).
2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-6 Expansion Bus Timing
Num
Characteristic
Symbol
1.0 MHz
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation (E-Clock
Frequency)
fo
dc
1.0
dc
2.0
dc
3.0
MHz
1
Cycle Time
tcyc
1000
—
500
—
333
—
ns
2
Pulse Width, E Low
PWEL = 1/2 tcyc - 23ns
PWEL
477
—
227
—
146
—
ns
3
Pulse Width, E High
PWEH = 1/2 tcyc - 28 ns
PWEH
472
—
222
—
141
—
ns
4A
4B
E and AS Rise Time
E and AS Fall Time
tr
tf
—
20
—
20
—
20
15
ns
9
Address Hold Time
tAH = 1/8 tcyc - 29.5 ns
(Note 1a)
tAH
95.5
—
33
—
26
—
ns
12
Non-Muxed Address Valid Time to E Rise
tAV = PWEL - (tASD + 80 ns)
(Note 1a)
tAV
281.5
—
94
—
54
—
ns
17
Read Data Setup Time
tDSR
30
—
30
—
30
—
ns
18
Read Data Hold Time (Max = tMAD)tDHR
0
145.5
0
83
0
51
ns
19
Write Data Delay Time
tDDW = 1/8 tcyc + 65.5 ns
(Note 1a)
tDDW
—
190.5
—
128
—
71
ns
21
Write Data Hold Time
tDHW = 1/8 tcyc - 30 ns
(Note 1a)
tDHW
95.5
—
33
—
26
—
ns
22
Muxed Address Valid Time to E Rise
tAVM = PWEL - (tASD + 90 ns) (Note 1a)
tAVM
271.5
—
84
—
54
—
ns
24
Muxed Address Valid Time to AS Fall
tASL = PWASH - 70 ns
tASL
151
—
26
—
13
—
ns
25
Muxed Address Hold Time
tAHL = 1/8 tcyc - 30 ns
(Note 1b)
tAHL
95.5
—
33
—
31
—
ns
26
Delay Time, E to AS Rise
tASD = 1/8 tcyc - 5 ns
(Note 1a)
tASD
115.5
—
53
—
31
—
ns
27
Pulse Width, AS High
PWASH = 1/4 tcyc - 30 ns
PWASH
221
—
96
—
63
—
ns
28
Delay Time, AS to E Rise
tASED = 1/8 tcyc - 5 ns
(Note 1b)
tASED
115.5
—
53
—
31
—
ns
29
MPU Address Access Time
(Note 1a)
tACCA = tcyc – (PWEL– tAVM) – tDSR–tf
tACCA
744.5
—
307
—
196
—
ns
35
MPU Access Time
tACCE = PWEH - tDSR
tACCE
—
442
—
192
—
111
ns
36
Muxed Address Delay
(Previous Cycle MPU Read)
tMAD = tASD + 30 ns(Note 1a)
tMAD
145.5
—
83
—
51
—
ns
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