參數(shù)資料
型號： MC68HC705SP7CP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 16/164頁
文件大?。?/td> 1165K
代理商： MC68HC705SP7CP
Programmable Timer
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
112
Freescale Semiconductor
11.6 Timer Control Register
The timer control register (TCR) shown in Figure 11-10, performs the following functions:
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag
bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active match of the output compare function. Reset
clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
Table 11-1. Output Compare Initialization Example
9B
...
B7
B6
BF
...
9A
16
13
17
SEI
...
STA
LDA
STX
...
CLI
OCRH
TSR
OCRL
DISABLE INTERRUPTS
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
ENABLE INTERRUPTS
Address:
$0012
Bit 7
654321
Bit 0
Read:
ICIE
OCIE
TOIE
000
IEDG
OLVL
Write:
Reset:
000000
U
0
= Unimplemented
U = Unaffected
Figure 11-10. Timer Control Register (TCR)
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