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參數(shù)資料
| 型號(hào)： | MC68HC705RC17P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.097 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 96/126頁 |
| 文件大?。?/td> | 3079K |
| 代理商： | MC68HC705RC17P |
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Carrier Modulator Transmitter (CMT)
Carrier Generator
MC68HC705RC17 — Rev. 2.0
General Release Specification
Carrier Modulator Transmitter (CMT)
NON-DISCLOSURE
AGREEMENT
REQUIRED
PH0–PH5 and PL0–PL5 — Primary Carrier High
and Low Time Data Values
When selected, these bits contain the number of input clocks required
to generate the carrier high and low time periods. When operating in
time mode (see 9.5.1 Time Mode), this register pair is always
selected. When operating in FSK mode (see 9.5.2 FSK Mode), this
register pair and the secondary register pair are alternately selected
under control of the modulator. The primary carrier high and low time
values are undefined out of reset. These bits must be written to non-
zero values before the carrier generator is enabled to avoid spurious
results.
NOTE:
Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will
also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear,
the IRO latch value appears on the IRO output pin. Care should be taken
that bit 7 of the data to be written to CHR1 or CHL1 should contain the
desired state of the IRO latch.
SH0–SH5 and SL0–SL5 — Secondary Carrier High
and Low Time Data Values
When selected, these bits contain the number of input clocks required
to generate the carrier high and low time periods. When operating in
time mode (see 9.5.1 Time Mode), this register pair is never selected.
When operating in FSK mode (see 9.5.2 FSK Mode), this register pair
and the secondary register pair are alternately selected under control
of the modulator. The secondary carrier high and low time values are
undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
IROLN and IROLP — IRO Latch Control
Reading IROLN or IROLP reads the state of the IRO latch. Writing
IROLN updates the IRO latch with the data being written on the
negative edge of the internal processor clock (fosc/2). Writing IROLP
updates the IRO latch on the positive edge of the internal processor
clock; for example, one fosc period later. The IRO latch is clear out of
reset.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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